1. Field of Invention
The present invention relates to a method for fabricating an integrated circuit (IC). More particularly, the present invention relates to a fabrication method for a gate structure having gate dielectric layers of different thicknesses.
2. Description of Related Art
Commonly on the same chip, it is necessary to equip some circuits with a low voltage (LV) device and a high voltage (HV) device. For example, an erasable programmable read only memory (EPROM) has a HV transistor for programming and a LV logic device which requires the HV transistor to process a higher external power supply voltage. Since these two devices operate with different voltages, gate dielectric layers of different thicknesses are made to accommodate their different voltage needs. In particular, the HV transistor needs a thicker gate dielectric layer for accepting a higher voltage, while the LV transistor has a thinner gate dielectric layer. Besides EPROM, ULSI development in the future may produce several different voltages to be applied to the same chip. Thus, according to the oxide reliability, gate dielectric layers having different thicknesses are needed in response to different voltages.
FIGS. 1A to 1D are schematic, cross-sectional diagrams illustrating a conventional method for fabricating a gate structure having gate dielectric layers having different thicknesses.
Referring to FIG. 1A, an oxide layer 108 is formed on a substrate 100 of a flash memory region 102, a HV region 104, and a LV region 106. A polysilicon layer (not shown) is formed on the oxide layer 108 and defined so that a floating gate 110 of the flash memory is formed only on the substrate 100 of the flash memory region 102. An oxide-nitride oxide (ONO) layer (not shown) is formed on the substrate 100, followed by forming a patterned photoresist (not shown) on the ONO layer. The ONO layer is defined to form an ONO dielectric layer 112 which covers the floating gate 110 on the substrate 100 of the flash memory region 102. The oxide layer 108 on the substrate of the HV region 104 and the LV region 106 is then removed, while the patterned photoresist is also removed.
Referring to FIG. 1B, an oxidation process is performed, so that an oxide layer 114 is formed on the substrate 100 of the HV region 104 and the LV region 106.
Referring to FIG. 1C, a patterned photoresist (not shown) is formed to cover the oxide layer 114 in the HV region 106 and the ONO dielectric layer 112 in the flash memory region 102, while the oxide layer 114 in the LV region 106 is left exposed. With the patterned photoresist serving as an etching mask, the oxide layer 114 in the LV region 106 is removed until the surface of the substrate 100 in the LV region 106 is exposed. The patterned photoresist is removed to expose the oxide layer 114 in the HV region 104. An oxidation process is further performed to form an oxide layer 118 on the oxide layer 114 in the HV region 104 and the substrate 100 in the LV region 106. To simplify the description, the oxide layers 114 and 118 in the HV region are generally known as an oxide layer 116.
Referring to FIG. 1D, a polysilicon layer (not shown) is formed on the substrate 100. The polysilicon layer, the oxide layer 116 in the HV region 104, and the oxide layer 118 in the LV region 106 are patterned so as to form a control gate 120a on the ONO dielectric layer 112 of the flash memory region 102. Meanwhile, a HV gate structure 122a having a gate electrode 120b and a gate oxide layer 116a is formed in the HV region 104, and a LV gate structure 122b having a gate electrode 120c and a gate oxide layer 118b is formed in the LV region 106.
Conventionally, during the formation of the gate dielectric layers having different thicknesses, steps for forming and removing the patterned photoresist have to be repeated several times on the ONO dielectric layer and the oxide layers 108, 114, in order to obtain gate dielectric layers having different thicknesses. However, as these steps are repeated several times before formation of the control gate 120a, the gate electrodes 120b, 120c, the ONO dielectric layer 112 and the oxide layers 108, 114 are contaminated by the patterned photoresists. This has made it difficult to control the quality of the ONO dielectric layer 112 and the oxide layers 108, 114. The gate oxide layer 116a, in particular suffers from poor quality after several episodes of contamination by patterned photoresist. Thus, the gate dielectric layer of the device is unable to withstand a breakdown produced by the set voltage, leading to a reduction in the reliability of the gate dielectric layer. Furthermore, the control gate 120a is damaged by etching and oxygen diffusion in the subsequent photolithographic etching and thermal oxidation.